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Chapter 7: RS-232 Serial Port
turn, converts the logic value to the appropriate RS-232 voltage level. Likewise, the Maxim
device converts the RS-232 serial input data to LVTTL levels for the FPGA. A series resistor
between the Maxim output pin and the FPGA’s RXD pin protects against accidental logic
conflicts. A detailed schematic appears in Figure A-7 .
Hardware flow control is not supported on the connector. The port’s DCD, DTR, and DSR
signals connect together, as shown in Figure 7-1 . Similarly, the port’s RTS and CTS signals
connect together.
The FPGA connections to the Maxim RS-232 translator appear in Table 7-1 .
Table 7-1:
Accessory Port Connections to the Spartan-3 FPGA
Signal
RXD
TXD
RXD-A
TXD-A
FPGA Pin
T13
R13
N10
T14
An auxiliary RS-232 serial channel from the Maxim device is available on two 0.1-inch
stake pins, indicated as J1 in the schematic and 8 in Figure 1-2 . The J1 stake pins are in
the lower left corner of the board, to the right of the DB9 serial connector, below the Maxim
RS-232 voltage translator, and to the left of the individual LEDs. The transmitter output
from the Maxim device drives the bottom stake pin while the receiver input connects to the
top stake pin.
The FPGA auxiliary RS-232 connections to the Maxim device appear in Table 7-1 with
signals RXD-A and TXD-A. Ignore the pin numbers listed on the silkscreen markings next
to the stake pins as these apply to the connections to the DB9 connector.
Place a jumper across the stake pins for an easy loop-back test. Alternately, create custom
serial ports by attaching the stake pins to other types of serial connectors such as male or
female DB9 or DB25 cable connectors or even create null modem connections.
34
www.xilinx.com
Spartan-3 FPGA Starter Kit Board User Guide
UG130 (v1.2) June 20, 2008
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